Nowadays, use of integrated circuit (IC) devices is ubiquitous. It is common that an IC device provides both analog and digital functions in a single package. For example, an IC device for a digital signal processing application typically includes analog amplifiers, e.g., one or more operational amplifiers (op amps), and digital circuits for processing an input signal.
A typical op amp is realized in an IC device using field effect transistors (FETs), e.g., metal-oxide semiconductor FETs (MOSFETs). Such an op amp comprises a current-mirror circuit, and a differential amplifier which receives inverting and non-inverting input signals to the op amp, respectively. In the typical op amp, a first FET in the current-mirror circuit is connected to at least a second FET in the differential amplifier to provide a desired bias current to the second FET. The first FET operates in a saturation mode, and the drain current thereof is constant and repetitive of a reference current provided in the current-mirror circuit.
Ideally, an op amp imparts a large gain, referred to as a "differential gain," to only the difference between the signal levels of the inverting and non-inverting input signals. However, in practice, the op amp also imparts another gain, referred to as a "common-mode gain," to a common-mode signal whose signal level equals the average of those of the inverting and non-inverting input signals. A common-mode rejection ratio (CMRR) which is defined as a ratio of the differential gain to the common-mode gain is often used as a figure of merit for the op amp. Since the output of an ideal op amp varies only with the aforementioned difference and is totally independent of the common-mode signal level, the CMRR of the ideal op amp is infinitely large, with the common-mode gain being zero.
As IC technology advances, the size limit, known as the "minimum feature size," of the circuit element s including FETs in an IC device decreases. Accordingly, the size of the circuit elements in the IC device is reduced to save space. As a result, the voltage of the power supply to the device needs to be reduced, stemming from the fact that the electric fields within the FETs in an IC device increase inversely with the size thereof. A lower power supply voltage reduces such electric fields which would otherwise cause an undesirable or even destructive current discharge within the FETs. Moreover, a lower power supply voltage causes lower power consumption in the IC device, which is desirable especially when the device is employed in a battery powered apparatus, e.g., a wireless telephone handset. Since the battery in such an apparatus has a limited capacity, the lifetime of the battery before replacement or recharging thereof increases as the power consumption of the IC device decreases. Thus, as the IC technology progresses to "0.1 .mu.m" technology in the near future, it is anticipated that the power supply voltage is going to be reduced from about 3 volts presently to about 1 volt.